APPLICATION OF GENETIC ALGORITHM FOR SWITCH LEVEL FAULT FINDING IN INTEGRATED CIRCUITS

Abstract

The paper describes an approach for the generation of deterministic test pattern generator logic. This approach employs a genetic algorithm that searches for an acceptable practical solution in a large space of implementation. Its effectiveness (in terms of result quality and CPU time requirement) for circuits previously unmanageable is illustrated. The flexibility of the new approach enables users to easily trade off fault coverage and CPU time to suit their needs.