Design of Instruction Fetch Unit and ALU for Pipelined RISC Processor

Abstract

Pipelining is a concept which improves the performance of processor. A five stage pipelined RISC processor has stages as instruction fetch, decode, execute, memory, write back. RISC has a simpler and faster instruction set architecture. The aim of paper is to design instruction fetch unit and ALU which are part of RISC processor architecture. Instruction fetch is designed to read the instructions present in memory. ALU is in the execution stage of pipelining which performs all computations i.e. arithmetic and logical operations. Xilinx 8.1i is used to simulate the design using VHDL language