Optimization Of Cmos Circuits By Using Quaternary Logic LUT

Abstract

vNow a days due to Interconnections the delay will increase in  design of a circuit. The more number of interconnections leads to increase in  the area of the circuit due to this the power consumption also more in COMS digital circuits. Multiple-valued logic can reduce the  average power required for level transitions and reduces the number of  interconnections for the design, hence also reducing the effects of interconnections on overall power consumption. In this paper, we propose quaternary lookup table (LUT) architecture was designed to replace or complement binary LUTs in field programmable gate arrays. The circuit is implemented with the CMOS processes, with a single voltage supply and voltage mode structures.