Design And Implementation Of High Efficient And Performance Of Modified Adder Circuit Using 128 Bit CSLA And BEC Adder For Filter Design

Abstract

Low Power VLSI is the major area in VLSI design to develop the product in smart way.  High performance is the keystone of the designer’s idea.  Performance depends upon the speed, reduce-in-delay, less power consumption and majorly cost.  In low power VLSI design, the contribution of adder is another platform.  Design of an adder is to be more efficient and at the same time the internal parameters such as area, power, delay, cost to be monitor.  Along with the benefits of super-fast performance the reduction of delay is a big advantage of using these types of adders.  On the other hand, the formations of different inputs and to process those inputs are the difficult to implement.   To overcome those difficulties, BEC based CSA are used.  To process a complexity mathematical inputs like squaring of inputs some special circuit are to be use.  Such a special circuit is the SQRT and along with CSLA it is called as SQRT-CSLA.  Discussion is taken place how to implement the SQRT-CSLA to analysis the practical values.  ASIC, SOC implementation is most popular in this type of implementation. In an existing methodology, it was analysed that the synthesis by ASIC results BEC-based SQRT-CSLA design involves 48% more ADP and consumes 50% more energy than the proposed SQRT-CSLA, on average, for different bit-widths.  We are focusing on this point, how to maximize the efficiency by utilize the power less and maximum result in the output.  Also, in an existing system the implementation is going with 64 bit widths as maximum and this clearly describes the factor how increase of the product efficiency took place.  But in our proposed methodology, we are going to adopt the processing bits of the range 128 bits