A Design of Low Power Low Area High Speed Full Adder Using GDI Technique

Abstract

Full Adder is the basic building block for various arithmetic circuits such as compressors, multipliers, comparators and so on. 1-bit Full Adder cell is the important and basic block of an arithmetic unit of a system. Hence in order to improve the performance of the digital computer system one  must improve the basic 1-bit full adder cell. In this, Full Adder is designed by using Hybrid-CMOS logic style. Hybrid designs are used to build a low power Full Adder cell. In the hybrid logic style more than one network is present. In general, it consists of three modules. Here we proposed the new Full Adder design by using the GDI (Gate Diffusion Index/Input) technique.GDI is a new method for reducing the power consumption, propagation delay, with less transistor count and power delay product (PDP).The simulation results are carried out on Tanner EDA tool. The simulation shows that the design has more efficient with less area, less power consumption and high  speed as compared to CMOS techniques.