A Soc Trojan Virus Detector And Corrector Using Multiple Monitoring Schemes

Abstract

A design of 16 bit processor is programmed in VHDL. The processor module is added with extra hardware logic calle d Trojan.A fault bit pattern is injected into the circuit along with the processor clock. The fault bit patterns triggers the extra hardware hidden in the processor that can be detected by verifying the output result from memory and CPU