Implementation of CMOS circuits In Logic optimization using logical effort technique

Abstract

The method of logical effort is an easy way to estimate delay and dynamic power in a CMOS circuit. We can select the fastest candidate by comparing delay estimates of different logic structures. The method also specifies the proper number of logic gates on a path and the best transistor sizes for the logic gates. Because the method is easy to use, it is ideal for evaluating alternatives in the early stages of a design and provides a good starting point for more intricate optimizations. In proposed work, the implementation of logical effort technique in static CMOS circuits like conventional adder, array multiplier, decoder and multiplexer occurred. So if its transistors sizing changed or adjusted such that its delay and PDP reduce then as a result of this bigger circuits also get the benefit of this changes