An Efficient Design of Parallel Pipelined FFT Architecture

Abstract

This paper presents a new parallel pipelined architecture to compute Discrete Fourier Transform (DFT) using FFT architecture. This particular architecture uses folding transformation technique as well as register minimization technique for the design of FFT architecture. Novel FFT architectures for the computation of complex and real valued signals are derived. Pipelining is used to reduce the power consumption. Parallel processing and pipelining exploits concurrency. Parallel processing also aids to the reduction of power consumption by reducing the supply voltage. The power consumption is reduced very effectively using the parallel architecture. This paper also includes various techniques to reduce the computation time and power using different types of multipliers.