Exploiting a Low Power Self Timed Ternary CAM Architecture Using RWOS Mechanism

Abstract

Content addressable memories are mostly used in computer networking devices. Power consumption is a major problem for these memories because of the parallel search operation. When compared to binary content addressable memories the mask cell increases the complexity and number of transistors. This paper introduces a new architecture for ternary content addressable memories. The proposed architecture called dual TCAM modifies the mask cell configuration so that the area and power consumption of the design can considerably be reduced. The search output from two CAM cells is used in the mask cell to work as a TCAM. As design example, a 8 × 4 bit TCAM is implemented and simulated by Tanner EDA Tool. The proposed TCAM achieves significant reduction in terms of power and number of transistors.