A Novel Power Saving Approach for Residue Number System Moduli Set Based On Fast Sign Detection Algorithm (International Journal of Engineering and Computer Science, 2015)
Although lot of research done o residue number system to save power but still it is considered as concerned area in the field of VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS  the proposed method presents an sign detection unit offers significant savings in delay, area and power compared with the sign detection units and recorded good performance over traditional approaches. The processing’s of the proposed work is performed in two steps namely, first, a sign detection algorithm for the restricted moduli set is described. The new algorithm allows for parallel implementation and consists exclusively of modulo 2n additions. Then, a sign detection unit for the moduli set {2n+1 − 1, 2n − 1, 2n} is proposed based on the new sign detection algorithm. The unit can be implemented using one carry save adder, one comparator and one prefix adder First, a sign detection algorithm for the restricted moduli set is described. The new algorithm allows for parallel implementation and consists exclusively of modulo 2n additions. Then, a sign detection unit for the moduli set {2n+1 − 1, 2n − 1, 2n} is proposed based on the new sign detection algorithm. The unit can be implemented using one carry save adder, one comparator and one prefix adder. Finally the experimental results shows that the proposed work offers 63.8%, 44.9%, and 67.6% savings on average in area, delay and power, respectively, compared with a unit based on one of the best sign detection algorithm.