Implementation Of Clock Gating Logic By Matching Factored Forms (International Journal of Engineering and Computer Science, 2018)
Clock gating is one among the most widespread circuit technique to scale back power consumption. Clock gating is sometimes done at the register transfer level (RTL). Automatic synthesis of clock gating in gate level has been less explored, however it's certainly additional convenient to designers.Clock gating consists of 2 steps: extraction of gating conditions by merging gating conditions of individual flip-flops, implementation of the gating conditions with minimum quantity of further gates.In this paper,We show a way to do  factored form matching, within which gating operates in factored kinds ar matched, as way as possible, with factored kinds of the mathematician functions of existing combinable nodes within the circuit; further gates are then introduced, however just for the portion of gating functions that don't seem to be matched. sturdy matching identifies matches that ar explicitly gift within the factored forms, and weak matching seeks matches that ar inexplicit the logic and so are tougher to get.