Review on 32-Bit IEEE 754 Complex Number Multiplier Based on FFT Architecture using BOOTH Algorithm (International Journal of Engineering and Computer Science, 2017)
In this paper, we have shown an review of High Speed, less power and less delay 32-bit IEEE 754 Floating Point Complex Multiplier using Booth Algorithm which includes 32-bit Floating Point Adder, Subtractor and Multiplier. Multiplication is an important fundamental function in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform (FFT), filtering and in microprocessors in its arithmetic and logic unit (ALU). Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. The main objective of this research is to reduce delay, power and to increase the speed. The coding will be done in VHDL, synthesis and simulation will be done using Xilinx ISE simulator.