9-Transistor Full Adder Design For Area Minimization (International Journal of Engineering and Computer Science, 2013)
The design of a new 9-transistors full adder which is simulated at 22nm CMOS technology. The design is based on a 3-transistor XOR Gate, two 2X1 multiplexers and a CMOS inverter. The main objectives to design this circuit are low power and small size of full adder.various methods are available for making full adder using more no. of transistor designing but these captured more area on si chip. So our design required less area using small building blocks. The design performance is analysed on Microwind Layout Editor on 22nm Fabrication Technology.