Novel Technique for Parallel Pipeline Double Precision IEEE-754 Floating Point Adder (International Journal of Engineering and Computer Science, 2015)
The Floating Point Additions are critical to implement on FPGAs due to their complexity of their algorithms in hard real-time due to excessive computational burden associated with repeated calculations with high precision numbers. Thus, many scientific problems requires floating point arithmetic with high level of accuracy in their calculations. Moreover, at the hardware level, any basic addition or subtraction circuit has to incorporate the alignment of the significands. This Paper represents Novel technique for implementation of parallel pipeline Double precision IEEE-754 floating point adder that can complete a operation in two clock cycle. This kind of technique can be very useful for parallelism of FPGA device and this proposed technique can exhibits improvement in latency and also in operational chip area management. The proposed double precision floating point adder has been implemented with XC2V6000 and XC3SI500 Xilinx FPGA Device.