High Speed Fused Add-Multiply Operator Design Based On SQRT-CSLA Adder (International Journal of Engineering and Computer Science, 2015)
Digital Signal Processing (DSP) applications involve        various complex operations. This paper deals with the high speed operation in the design of the Fused-Add multiply operator for increasing the Performance. This includes the techniques to implement the direct recoding of the sum of two numbers  in the Modified Booth (MB) form and involves the high speed addition using the SQRT-CSLA  adder. This paper makes use of all the three structured and efficient recoding technique by means of three different schemes available  in FAM designs. In comparison to the existing  schemes, the proposed technique yields considerable reductions in terms of critical delay, hardware complexity and power consumption of the FAM unit.