An Efficient Technique for Parallel CRC Generation (International Journal of Engineering and Computer Science, 2014)
Cyclic Redundancy Check is playing a vital role in the networking environment to detect the errors. With challenging speed of transmitting data and to synchronize with speed, it’s necessary to increase speed of CRC generation. This paper presents 64 bits parallel CRC architecture based on F-matrix with order of generator polynomial is 32. Implemented design is hardware efficient and requires 50% less cycles to generate CRC with same order of generator polynomial. CRC32 bit is used in Ethernet frame for error detection. The whole design is functionally developed and verified using Xilinx ISE 12.3i Simulator.