(untitled) (International Journal of Engineering and Computer Science, 2015)
Multiplication is one of the important operation in most digital signal processing (DSP) applications. Sometimes the performances of DSP applications is dominated by the speed at which a multiplication operation can be executed. The main goal to design the multiplier is to reduce the delay and power dissipation of a multiplier. Hence improved vedic multiplier is designed to increase the efficiency of the system. Implementing this vedic multiplier with reversible logic additional reduces power dissipation. Vedic multiplier is designed using one of the vedic algorithm," Nikhilam Navatascaram Dasatah which is mean by “All from Nine and the last from Ten”. This method is implemented using reversible logic gates to reduce the power dissipation and number of logic gates. The synthesis and simulation of Nikhilam Reversible algorithm is obtained by using Xilinx ISE 13.2, implementation and detailed design analysis results are given in the paper.