(untitled) (International Journal of Engineering and Computer Science, 2014)
The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the Silicon dioxide (SiO2) layer used as a gate dielectric becoming so thin so it produces the tunnelling current leakage, high power consumption and produces high heat when scaling of the transistor. It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (κ) or ‘high K’ gate oxides. A technique has been developed to fabricate a Thin Film Transistors (TFT) using stacked high- κ nanomaterials. Here in this work using TiO2, and ZrO2 as high-κ dielectric nanomaterials, ITO/PET substrate which is flexible, and HMDS as a semiconducting layer provides high performance to the device. Through this proposed approach the above problems are solved and the transistor could be shrunk below 32 nm