(untitled) (International Journal of Engineering and Computer Science, 2013)
Power is arguably the critical resource in VLSI system design today. In this paper a brief review is discussed about drowsy cache & also about the “Variation Trained Drowsy Cache” (VTD-Cache) architecture. As process technology scales down, leakage power consumption becomes comparable to dynamic power consumption. The drowsy cache technique is known as one of the most popular techniques for reducing the leakage power consumption in the data cache. However, the drowsy cache is reported to degrade the processor performance significantly. In this paper VTD-Cache allows for a significant reduction of around 50% in power consumption while addressing reliability issues raised by memory cell process variability. By managing voltage scaling at a very fine granularity, each cache way can be sourced at a different voltage where the selection of voltage levels depends on both the vulnerability of the memory cells in that cache way to process variation and the likelihood of access to that cache location. The novel and modular architecture of the VTD-Cache and its associated controller makes it easy to be implemented in memory compilers with a small area and power overhead. This total process is studied with different diagrams ,schematics using Xilinx 14.5 software.