(untitled) (International Journal of Engineering and Computer Science, 2018)
Memory arrays are an essential building block in any digital system. This paper presents the implementation of an SRAM array to avoid the half selected column disturbance when the cell has separate write signal (data aware 9T cell). The array of different size is simulated in terms of power, delay and process variation with and without peripheral circuits and results are compared with the conventional 6T cell array. The proposed array consumes lower power compared to the 6T during read/write and hold mode. The power reduction is due to forbidden discharging at bit-lines during write operation, control of leakage current due to proper array implementation and lower voltage drop on read bit-line. The write delay is improved due to separate write signal. The read delay is larger than 6T array which can be reduced by independently optimizing the read path or using read/write multiplexer at the local bit line due to signal HD in the array. During hold mode maximum 43% power saving is achieved compared to the 6T array. The proposed array implementation shows less variation with the threshold voltage