(untitled) (International Journal of Engineering and Computer Science, 2014)
The paper describes the development of FIR filters on Field programmable gate array (FPGAs) using FFT Algorithm. FIR filter has been designed and realized by FPGA for filtering the digital signal. The implementation of FIR filter on a Cyclone IV GX FPGA is considered. Presented soft core is the unit to perform the finite impulse response filter based on the Fast Fourier Transform (FFT). It performs the convolution of the unlimited signal sequence with the synthesized impulse response of the length of Ni=N/2 samples, where N = 64, 128, 256, 512, 1024. The data and coefficient widths are tunable in the range 8 to 18. The model is capable of performing filtering operations like low pass, high pass, band pass and band stop based on selection that is embedded into the design. The most basic functions required for nearly any signal processor include addition, multiplication and delays. Input data, output data, and coefficient widths are generics. The maximum sampling frequency Fs by N=1024 is less than Fclk/29. IP Corse has been used to filter the input data. The design is coded through VHDL (hardware descriptive language). To verify the designed outputs simulation, compilation and synthesis have been done.