(untitled) (International Journal of Engineering and Computer Science, 2016)
The power consumption and area reduction are the key challenges in the Very Large Scale Integration (VLSI) circuit design. Power consumption and Area reduction plays a major role in sequential circuit design. Shift register is the main building block in the VLSI circuits. The shift register is composed of clock inter connection network and timing elements such as flip-Flops and latches. The shift registers are design using edge triggered flip flops but the use of latches for shift register design also optimizes the area. This project introduces a low power and area efficient shift register using pulsed latch and pulse generation circuit. If the Flip-Flop is replaced with the pulsed latch the area and power consumption can be reduced to 50% in the shift register. For this design a non overlap clock pulses are used. This solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. To minimize power consumption various non overlap delayed pulsed clock signal design is proposed for data synchronization in an exceedingly multi bit shift register. The proposed system is designed by using a popular Schematic and layout capture tool with 90nm technology.