(untitled) (International Journal of Engineering and Computer Science, 2015)
This explicit pulse triggered flip flop consist of a pulse generator and a true single phase clock latch based on a signal feed through scheme. The pulse generator is built with two CMOS inverters along with transmission gate logic which reduces the complexity of the circuit. The Pulse generation logic used in the explicit mode by a single pulse generator is shared for many number of flip flop at a time result in reduction of power not only this overall transistor count and delay can also been reduced.. And this flip flop can achieve better D-Q delay and by using this explicit pulse triggered flip flop a synchronous counter is constructed and power dissipated is very less.