(untitled) (International Journal of Engineering and Computer Science, 2015)
In today’s modern system-on-chips , there are several intellectual properties on the system to provide different functionality. However, more complex communications on SoCs the harder at which the programmer could discover all errors before first silicon during its verification. Therefore, it provides a reconfigurable unit for recording the transactions between IPs and adopt logical vector clock as a time stamp of each trace. The programmable trigger unit in debugging node could be configured by the validation to cache their interest sequences of transaction. Because traces of transactions would have their own timestamp, during the post-silicon validation, finally it could reproduce the errors in faulty transactions between IPs and get more information for by passing or fixing the problems. In future, due to several entries of traces finally shrink observation window very quickly, it also implement a compressor to compress traces before it store them into trace buffer. Finally,experiments demonstrate that the proposed debugging architecture is capable of recording the critical transactions, and the proposed reconfigurable debugging unit whole debugging execution time can be reduced more than 80%.