(untitled) (International Journal of Engineering and Computer Science, 2017)
In this paper proposed power and area efficient discrete cosine transform (DCT) architecture for multimedia applications. This paper Implemented conventional DCT and multiplier less DCT‟s by less number of adders/subtracter and multipliers. Area and power achieved by reducing mathematical operations. Number of cells, cell area, internal power, net power, leakage power, switching power reduced compared to conventional DCT. Power delay product of both conventional DCT and multiplier less DCT‟s are 19.8mJ, 19.7mJ and 10.8 mJ respectively. The proposed DCT and conventional DCT are implemented on cadence RTL compiler 180nm.