(untitled) (International Journal of Engineering and Computer Science, 2014)
Multiplier is an important key element used for arithmetic operations in digital signal processor. Power consumption in multiplier is more when compared with adders and subtractors. So reducing the power consumption of multiplier makes a digital signal processor more efficient. A Wallace tree multiplier is an efficient high speed multiplier that multiplies two integers. Here a 4*4 Wallace tree multiplier is proposed with ten full adders. Each full adder used in this design has only nine transistor which is less in number when compared with the conventional full adders. Due to this the power consumption of full adder block is reduced, such that power consumption of 4*4 Wallace Tree Multiplier will be reduced. The proposed design is simulated using 0.12µm technology in Microwind 2 Tool and has achieved upto 50% power saving in comparison to the Wallace Tree Multiplier that has been designed using Conventional Full adder.