(untitled) (International Journal of Engineering and Computer Science, 2014)
Power dissipation is major area of concern in today’s CMOS technology. In this paper we present a six transistor (6T) Static Random Access Memory cell for low power applications. The proposed design has strong read static noise margin (SNM) and strong write ability. The impact of process variation on the different failure mechanism in SRAM cell is analyzed. A 32 bit SRAM with proposed and standard 6T bit cells is simulated and evaluated for read SNM, write ability and power. In the proposed 6T SRAM architecture intended for the advanced microprocessor cache market using 0.18um technology. The goal is to reduced power dissipation while maintaining competitive performance.